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// software and tools, and its AMPP partner logic functions, and any output 
// files from any of the foregoing (including device programming or simulation 
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// license agreement, including, without limitation, that your use is for the 
// sole purpose of programming logic devices manufactured by Intel and sold by 
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module vgpio_avc_map(
    input logic          clk,
    input logic          reset_n,
    // cpufpga vgpio fixed assignments
    input logic          espi_reset_n,//vGPIO reset source
    //  Reset
    input logic          PWRGD_AUX_PWRGD_CPU0_PLD,
    // GPO from master to slave
    output logic         FM_UPI_INIT_DONE,
    output logic         RES_140_2,
    output logic         FM_ADR_MODE0,
    output logic         FM_PERST_DELAY_SEL,
    // GPI from slave to master,
    input  logic         FM_PASSWORD_CLEAR_N,
    input  logic         FM_BOARD_SKU_ID0,
    input  logic         FM_BOARD_SKU_ID1,
    input  logic         FM_BOARD_SKU_ID2,
    input  logic         FM_BOARD_SKU_ID3,
    input  logic         FM_BOARD_SKU_ID4,
    input  logic         FM_BOARD_SKU_ID5,
    input  logic         RES_147_2,
    input  logic         RES_147_3,
    input  logic         FM_BOARD_REV_ID0,
    input  logic         FM_BOARD_REV_ID1,
    input  logic         FM_BOARD_REV_ID2,
    input  logic         FM_RST_PERST_BIT0,
    input  logic         FM_RISER2_WIDTH,
    input  logic         FM_RISER2_MODE,
    input  logic         FM_RISER3_WIDTH,
    input  logic         FM_RISER3_MODE,
    input  logic         FM_CPU0_INTR_PRSNT_N,
    input  logic         FM_CPU1_INTR_PRSNT_N,
    input  logic         FM_CPU0_INTR_ID,
    input  logic         FM_CPU1_INTR_ID,
    input  logic         FM_PCIE_EV_BIF_EN,
    input  logic         H_CPU0_ERR0_LVC1_N,
    input  logic         FM_SFFX4_EXPCARD_IO_B_0,
    // Generic IO ports from generic map module
    input  logic [511:0] vgp_out,      // top level GP inputs
    output logic [511:0] vgp_in        // top level GP outputs
);

// Register outputs 2x to ease timing
logic [511:0] vgp_out_reg;
always @(posedge clk ) begin
    vgp_out_reg          <= vgp_out;
    FM_UPI_INIT_DONE     <= vgp_out_reg[64];
    FM_ADR_MODE0         <= vgp_out_reg[65];
    RES_140_2            <= vgp_out_reg[66];
    FM_PERST_DELAY_SEL   <= vgp_out_reg[67];
end

logic [511:0] vgp_in_meta;
// Synchronize inputs

always @(posedge clk or negedge reset_n) begin
    if(!reset_n) begin
        vgp_in_meta              <= 512'b0;
        vgp_in                   <= 512'b0;
    end else begin
        if (PWRGD_AUX_PWRGD_CPU0_PLD) begin
            vgp_in_meta[67:0]    <= '0;
            vgp_in_meta[68]      <= FM_PASSWORD_CLEAR_N;
            vgp_in_meta[69]      <= FM_BOARD_SKU_ID0;
            vgp_in_meta[70]      <= FM_BOARD_SKU_ID1;
            vgp_in_meta[71]      <= FM_BOARD_SKU_ID2;
            vgp_in_meta[72]      <= FM_BOARD_SKU_ID3;
            vgp_in_meta[73]      <= FM_BOARD_SKU_ID4;
            vgp_in_meta[74]      <= FM_BOARD_SKU_ID5;
            vgp_in_meta[75]      <= FM_BOARD_REV_ID0;
            vgp_in_meta[76]      <= FM_BOARD_REV_ID1;
            vgp_in_meta[77]      <= FM_BOARD_REV_ID2;
            vgp_in_meta[78]      <= RES_147_2;
            vgp_in_meta[79]      <= RES_147_3;
            vgp_in_meta[80]      <= FM_PCIE_EV_BIF_EN;
            vgp_in_meta[81]      <= FM_RISER2_WIDTH;
            vgp_in_meta[82]      <= FM_RISER3_WIDTH;
            vgp_in_meta[83]      <= FM_RISER2_MODE;
            vgp_in_meta[84]      <= FM_RISER3_MODE;
            vgp_in_meta[85]      <= FM_SFFX4_EXPCARD_IO_B_0;
            vgp_in_meta[86]      <= H_CPU0_ERR0_LVC1_N;
            vgp_in_meta[87]      <= FM_RST_PERST_BIT0;
            vgp_in_meta[123:88]  <= '0;
            vgp_in_meta[124]     <= FM_CPU0_INTR_PRSNT_N;
            vgp_in_meta[125]     <= FM_CPU1_INTR_PRSNT_N;
            vgp_in_meta[126]     <= FM_CPU0_INTR_ID;
            vgp_in_meta[127]     <= FM_CPU1_INTR_ID;
            vgp_in_meta[511:128] <= '0;
            vgp_in               <= vgp_in_meta;
        end else begin
            vgp_in_meta[67:0]    <= 68'b0;
            vgp_in_meta[68]      <= 1'b1;
            vgp_in_meta[85:69]   <= 17'b0;
            vgp_in_meta[86]      <= 1'b1;
            vgp_in_meta[123:87]  <= 37'b0;
            vgp_in_meta[125:124] <= 2'b11;
            vgp_in_meta[511:126] <= 386'b0;
            vgp_in[67:0]    <= 68'b0;
            vgp_in[68]      <= 1'b1;
            vgp_in[85:69]   <= 17'b0;
            vgp_in[86]      <= 1'b1;
            vgp_in[123:87]  <= 37'b0;
            vgp_in[125:124] <= 2'b11;
            vgp_in[511:126] <= 386'b0;
        end
    end
end


endmodule
